`timescale 1ns/1ps

module tb_ad_3pa1030;

parameter mux_num = 10;
parameter work_clk = 300_000_000;
parameter ad_freq = 15_000;
parameter start_trigger_pos = 2;

reg clk;
reg rst;
reg [9:0] ad_3pa1030_ch;
wire datin_bram_w_en;
wire [clogb2(mux_num) - 1:0] datin_bram_w_addr;
wire [9:0] datin_bram_w_data;
wire datin_bram_w_we;
wire start;

ad_3pa1030 #(
  .mux_num(mux_num),
  .work_clk(work_clk),
  .ad_freq(ad_freq),
  .start_trigger_pos(start_trigger_pos)
) uut (
  .clk(clk),
  .rst(rst),
  .ad_3pa1030_ch(ad_3pa1030_ch),
  .datin_bram_w_en(datin_bram_w_en),
  .datin_bram_w_addr(datin_bram_w_addr),
  .datin_bram_w_data(datin_bram_w_data),
  .datin_bram_w_we(datin_bram_w_we),
  .start(start)
);

// 生成时钟
initial clk = 0;
always #(1_000_000_000 / (2 * work_clk)) clk = ~clk; // 300MHz 时钟

// 初始化和激励
initial begin
  rst = 1;
  ad_3pa1030_ch = 0;
  #(100);         // 等待一些时间
  rst = 0;

  // 模拟采样数据持续变化
  forever begin
    @(posedge clk);
    ad_3pa1030_ch = ad_3pa1030_ch + 1;
  end
end

// 显示信号变化
initial begin
  $display("Time\t\tclk\tw_en\taddr\tdata\tstart");
  $monitor("%t\t%b\t%b\t%d\t%d\t%b", $time, clk, datin_bram_w_en, datin_bram_w_addr, datin_bram_w_data, start);
end

// 仿真时间
initial begin
  #(1_000_000_000 / ad_freq * mux_num * 5); // 采样5轮
  $finish;
end

function integer clogb2(input integer depth);
  integer tmp;
  begin
    tmp = depth;
    for (clogb2 = 0; tmp > 0; clogb2 = clogb2 + 1) 
      tmp = tmp >> 1;                          
  end
endfunction

endmodule
